Design And Implementation Of DDR2 SDRAM Controller Based On FPGA

Memory, as an important part of the electronic communications equipment, plays a key role in the entire system. The memory capacity and access speed have made further demands in order to meet some electronic product needs, such as multi-function, high performance, low power. DDR2(Double Data Rate) SDRAM(Synchronous Dynamic Random Access Memory) memory was widely used in the field of electronic communications, which has high read and write speed, large capacity, and high stability. Compared with other synchronous dynamic random access memory, DDR2 SDRAM has the highest cost performance. However, the operation on DDR2 SDRAM, which is quite complicated, needs a large number of parameters and complex schema category. To control DDR2 steadily and effectively. DDR2 SDRAM controller, which is reasonable and concise, designed in this paper. It can realize the reading and writing operation, which only need to connect the control signal and memory interface. Finally, this DDR2 controller could realize the basic function though the simulation software to verify.First of all, this paper had a detailed analysis of the working principle of DDR2 SDRAM, and learned its structure and signal of interface. On this basis, DDR2 SDRAM primary operation sequence and typical timing are given. Adopt the top-down designing method, the DDR2 controller design was divided into initialization module, reader control module, data channel module and refresh module. The initialization module was used for set the working mode of the memory. The reader module was used for data read and write operations. The data channel module finished reading and writing data. The refresh module was used for timing of the DDR2 SDRAM refresh. In the process of implementation, to complete the initialization module and reading-writing control module design by using the form of a state machine. In addition, FIFO is adopted to solve problems of different clock domains in the data access module. This module division made the system clear, and conducive to the code maintenance and debugging.In the end, the paper had set up a simulation and verification platform. The FPGA processor used XILINX Company providing XC6SLX75-3CFGG676 SPARTAN 6 series. The memory used Micron Company providing MT47H128M16-25 DDR2 SDRAM.Using the company’s own ISim simulation tools, I made the controller simulation for each operation and finished the verification on FPGA development board. One hand, I referred to the operating steps and timing requirements on the chip manual. On the other hand, I based on the simulation and verification results to prove the correctness of this design. Finally, the paper design provide a good foundation for the follow-up video transform system.