Research And Design Of A 10bit 50MSPs Pipeline ADC

With the fast development of semiconductor fabrication technology, more and more signal-processing activities are moving to the digital domain for its high reliability, high integration and low cost. Analog to Digital converters (ADCs) are bridges which connect digital signal and analog signal, ADC play an important role in modern signal-processing system. With the development of SOC technology, embedded ADC becomes one of the most important IP core. Nowadays, high speed, medium to low accuracy ADCs are widely used in disk input-output drive circuit, medical imaging instrument, communications equipment and so on. In these applications, ADCs face the problems of the tradeoff between speed, power consumption and accuracy. So the design of high speed, low power consumption, high accuracy ADC become a hot research.Compared to Other structures, Pipeline ADC can get highe speed and highe accuracy at the same time. A pipeline ADC is inherently a multistep amplitude quantizer in which digitization is performed by a cascade of many topologically similar or identical stages of low-resolution analog-to-digital encoders. Pipelining enables high conversion throughput by inserting analog registers, i.e., sample-and-hold amplifiers(SHAs), in between stages that allow a concurrent operation of all stages. This is done at the cost of an increased latency. Each stage output two kinds signal, one is digital signal, as one bit of the digital output, the other one is analog signal, as the input of the nest stage. The signal passed to the subsequent stage is the conversion residue of the current stage created by a digital-to-analog converter(DAC) and a subtraction circuit. The maximum swing of this residue signal is often brought back to the full-scale reference level with a precision amplifier. This keeps the signal level constant and allows the sharing of an identical reference throughout the pipeline stages. Breaking a high-resolution conversion into multiple steps greatly reduces the total number of comparators in contrast to a flash converter. In the limiting case, a 1-bit per stage pipeline ADC only needs N comparators to resolve an N-bit word as opposed to 2N comparators required by a flash converter. For medium to high resolution Nyquist applications, pipeline ADCs have been demonstrated to achieve the lowest power consumption at high conversion rates.The performance of the Pipeline ADC is largely determined by the speed and accuracy of the sample and hold circuit. The sample and hold circuit is inherently an op amp in feedback network. So how to design a high gain, high bandwidth op amp becomes the key of our design.With the development of CMOS processing technique, the size of MOS becomes smaller and the supply voltage become lower. This leads to smaller and lower power consumption, but also leads to higher design difficulty. In low supply analog integrate circuit, more and more designers use the gain-boosting op amp because its high swing and high bandwidth. In our ADC, we design a gain-boosting op amp which achieves a dc gain of 92dB, a unity gain frequency of 590MHz.This paper designs a 10 bit 50 MSPs Pipeline ADC, this ADC consist of Sample and Hold circuit(S/H), Sub-ADC, Sub-DAC, and Digital Correction circuit. This ADC has 9 stages, the former 8 stages use the 1.5 bit per stage structure, which is know to tolerate large comparator offsets; the last stage is a 2 bit Flash ADC, the Pipeline ADC also use a Digital Correction circuit to correct and synchronize the output of the Pipeline ADC. This Pipeline ADC uses the design method of stage scaling, which can largely reduce the power dissipation of the chip. In the Sample and Hold circuit, we use the gain boosting op amp, which improves the precision of the S/H circuit. This Pipeline ADC use the 0.18um CMOS technology, the supply voltage is 1.8V, the ADC can accept -1V to +1V fully differential input, the common mode input voltage is 0.9V. This design is finished in Cadence, the simulation tool is Spectre. Under 10MHz sine wave input, this ADC achieves ENOB( Effective Numbers Of Bits) of 9.98 bit, SNR(Signal to Noise Ratio) of 61.82dB, SFDR(Spurious Free Dynamic Range) of 76.18dB, the total power dissipation is 26mW.