The Research For A 100-MS/s Reconfigurable Pipelined A/D Converter

With the rapid development of semi-conductor technology, integrated circuit has stepped into a new era of system on chip (SoC). SoC requires the integration of analog circuits and digital circuits on a single chip. So it is very important to design a high performance A/D converter, which is based on standard CMOS technology. With the explosive development and wide use of wireless communication, imaging process and video process, A/D converter also trends to be high-speed high-resolution and low-power dissipation. Pipelined A/D converter has an excellent combination of high-resolution and high-precision; at the same time, it has a good trade-off between speed and power dissipation, so it is widely used. For the requirement of multi-standard transceiver of wireless LAN, this thesis will research for a 100-MHz sample/s reconfigurable pipelined A/D converter.firstly, this thesis chooses a 1.5 bit/stage pipelined A/D converter, whose power dissipation is very low at high sampling frequency. This structure not only could make the design of SubADC and SubDAC simply, but also could eliminate the offset of comparators by digital error correction circuit. Aiming at the fixed resolution and the ninth stage's digital output couldn't be corrected of the traditional 1.5 bit/stage pipelined structure, this thesis designs a reconfigurable pipelined A/D converter. In the reconfigurable pipelined structure, the first nine stages adopt the same structure, some of which are chosed to operate to achieve the different resolution (6~10-bit) by the reconfigurable control circuit, and the tenth stage just is a simple comparator, which is used to correct the digital output of the ninth stage. Secondly, this thesis analyzes the digital error correction theory of 10-bit 1.5 bit/stage pipelined A/D converter which couldn't detect the input signal's overflow. Then designs circuit and obtains an overflow detect signal which could detect whether the input signal is overflow. Finally this thesis analyzes the non-ideal characteristics of MOS sample-and-hold circuit. To reduce these non-ideal characteristics, this thesis adopts a CMOS full differential sample-and-hold circuit, which could reduce the effect of clock feedthrough and channel charge injection. Besides, in order to improve linearity of sample switch, designs a bootstrapped CMOS switch circuit.The whole system and digital error correction circuit are simulated in the simulink environment; at the same time, based on SMIC 0.18 um CMOS mixed-signal process model the switch circuit is simulated by using Hspice. And the results of simulation show that: the reconfigurable pipelined A/D converter could reconfigure its resolution from 6-bit to 10-bit and also could eliminate efficiently the offset error of comparators of each stage. The overflow detect signal OF could detect correctly whether the input signal is overflow. At 24.4140625 MHz input frequency and 100 MHz sampling frequency, the SFDR of bootstrapped CMOS switch circuit is about 80 dB, which is lower 20 dB than the common CMOS switch circuit.