Design And Implementation Of Timing Controllers Applied To TFT-LCD Systems

With the technology of Flat Panel Displayer (FPD) improved continually, FPD are used widely in many graphic and display fields, and taking place of CRT Displayer to become the mainstream equipment in display system. As one of the most important parts in FPD control IC, Timing Controllers bear responsibility for LCD systems'running well. The chip receives and process signals from Frond-end circuit, then generates control signals to assure that the LCD panel works well. In another words, the chip helps the Frond-end circuit and the LCD panel to communicate with each other. This thesis starts with introducing the function of Timing Controller in LCD system. It presents a whole ASIC design flow of a TCON chip and FPGA verification with TOP-Down design topology, based on the research of FPD's display theory and implement. This chip accepts different formats of video signals, and could apply in systems with various LCD panels.By researching and comparing with products both internal and overseas, first a structure of Timing Controller in theory is presented, then according to different applications, design TCON chips respectively. For medium and small-sized LCD systems, the detailed design and implement of the TCON chips are given. But for large-sized LCD systems, because of restriction on time and conditions in the lab, it only gives the theory of design and some basic research of key technology in the chips instead of the implement.In the thesis, the RTL code of Timing Controller chip is described by using Verilog HDL. In succession, the function verification and logic simulation by Mentor Graphics ModelSim (ver 6.0)and Synopsys VCS 6.0.1, including proposing a verification scheme, designing a FPGA verification PCB as well as implementation with Xilinx ISE Series 6.3i and FPGA Spartan-II xc2s200-pq208-5 are presented, and adjusting previous designs according to the verification results. Based on the FPGA verification results, synthesis and Static Timing Analysis of the design by Synopsys Design Compiler (ver X-2005.9) and Prime Time (ver X-2005.9-SP2)are given. The whole ASIC flow is accomplished successfully with the assistance of colleagues of Asian Microelectronic Company. Through the FPGA function verification, post layout simulation and simulation of the ASIC Chip, the TCON proposed in the thesis to meet the expected performance requirement of the system.