Static Timing Analysis And Design Of The High Performance Microprocessor IP Core

With the increase of circuit design complexity,integration and circuit performance requirements,along with the decrease of chip size,the demand for chip timing is getting higher and higher.Timing convergence is one of the most difficult problems.Timing analysis is a very important aspect of integrated circuit design.It is the method that checks if the chip works properly at the specific frequency.So that is also an important reference point of pre-tapeout.In order to ensure that the chip can work normally under the expected performance requirements,the timing verification must take into account a large number of factors.The purpose of this paper is to study the static timing analysis method suitable for large scale integrated circuit.It can check whether the timing of circuit design is accurate,and ensure that the circuit design can work normally under the required working frequency.Studying the basic situation of static timing analysis,including principle of static timing analysis,researching status domestic and abroad.Based on the IP(Internet Protocol)core of high-performance microprocessors,the following research is completed.Firstly,the timing model of each unit in the IP core of high-performance microprocessors is extracted.Different complex D flip-flop and domino structure need different approaches based on the Nanotime(NT)to solve complex topology recognition error,which improves the effectiveness of timing model.By the provided this paper,the effective timing model can be achieved.A complete inspection mechanism is established to ensure the accuracy of the liberty building.Secondly,timing verification of IP core use hierarchical processing method.Not only did the timing environment construction and constraint settings are completed,but also the timing of the gate level netlist with parasitic parameters is verified.According to the characteristics of the timing-violated path,the appropriate optimization method is used to fix the path.Thirdly,finished the formal verification to complete the pre fix netlist and post fix netlist,and ensure the functional consistency.