Design Of A 1GHz PLL With 0.18um CMOS Technology

Because of the rapid development of the wireless communication technology, the design and research of the integrated circuits in the related field has gained more and more attention in recent years, There are strict requirements to the clock generator. Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-appl -ied technique. There is a PLL (Phase Locked Loops) in system to get a high-stability low-noise high-frequency signal.A monolithic clock synthesis PLL, which is expected to be a reference 800MHz clock generator, has been designed and characterized in this paper. Because its low cost and easy of implementation, the frequency synthesizer has been designed in SMIC 0. 18μm CMOS technology and 1.8V supply voltage in this paper.The design method of Top to Down is used-from the system level to the circuit level has been done. Firstly, the whole structure of PLL is introduced. Then each module is separately described, different topology is balanced and the ones used in this design are presented. The PLL consists of a crystal oscillator, a frequency divider, a phase/frequency detector, a charge pump and a loop filter. Finally, layout and verification of PLL circuit is competed, the whole circuit has been simulated using Cadence Spectre.The simulation results show that the output frequency can be locked to 1GHz in SS, TT, FF corners. The phase noise at 1MHz frequency offset is -101dBc/Hz, -103dBc/Hz, -104dBc/Hz。The active chip area is less than 0.15mm , and the power consumption is only 16mW. All circuit undergoes simulation, accord with the design requirement, the test results of the whole PLL circuit validate our specifications. 2...