Research Of 10-bit 50MS/s Pipelined ADC For Embedded Use

The thesis presents the design of a 2.5V 50MS/s 10-bit pipelined Analog-to-Digital Converter (ADC) following an analysis on various A/D convert, a discussion on the development trend of ADC and a conclusion of the specialties of embedded ADC.It's a 1.5bit/stage pipeline ADC with 9 stages. In order to minimize the power consumption and layout size of the whole ADC, the operational amplifier sharing technique is used to decrease the number of OTA used; the sampling capacitors in each stage is scaled down gradually to decrease the load of the OTA .The ADC is implemented in Switch-Capacitor circuit. The following technologies are taken in the implementation: fully differential structure is used to maximize the signal amplitude and common noise rejection; rail to rail, high-gain OTA and CMOS switches are used in SC circuit, resulting in higher resolution, lower power dissipation and smaller size; the low power high speed dynamic comparators is used to keep the analog signal from pipeline stage stable during the high frequency sampling phase; the two-phase non-overlapping clock generator is designed to make full use of the holding time.This chip is designed in SMIC 0.25um single-poly five-metal standard CMOS process. The core die size is 0.3×0.6mm2. The power dissipation is 16.9mW with 2.5V power supply. Simulation results show that it achieves the SNDR of 55.3dB, a maximum DNL of 0.7 LSB, a maximum INL of 1.8 LSB for a 2.04MHz sinusoid input at full sampling rate.