Investigation On High Performance Pipeline A/D Converter For CMOS Image Sensor

Today, sensor technologies are becoming increasingly popular and are an area where ADCs play a major part. For the application of a high speed high dynamic range CMOS image sensor, ADCs with high speed and high resolution are required. The research tries to achieve a high performance pipeline ADC for the CMOS image senor. And the paper incudes the content as followed.First, a system model of 1.5b/stage pipeline ADC built in Matlab has been introduced. Non idealities such as thermal noise, comparator offset, and gain error of MDAC have been considered respectively in that model. And the connection between the circuit parameters and ADC system specs has been found by system model simulation. Some data has also been gained in that simulation to steer the detailed circuit design.Second, the macro system model has been segmented into some modules which include analog and digital part implemented in chartered 0.35um. In the analog part, the switch capacitor circuit has been optimized between its power and performance. In the digital part, the system timing has been carefully arranged by designing the clock generator. And the rational system timing guarantees the reliability of the system. In addition, some other assistant circuits such as latch array, adders are designed to complete the function or be a part of digital correction module.Third, layout has been carefully design since the pipeline ADC is a standard mixed signal system. Some technique has been used to consider the match and noise issue of the entire chip. And finally the simulation has been done in the Spectre and the ADC achieves the desired THD performance.The specific research contributions of this work include: (1) Optimize the system by system level simulation. (2) Optimize the SC circuit to minimize the power furthermore. (3) Use rational system timing to eliminate or alleviate the nonidealities. (4) Use constant VGS switch technique to get better performance. (5) Do Careful layout and rational floorplan to guarantee the performance when the chip is tapeout.