Test Research Based On RAS Structure

The VLSI technology has advanced to the era of the deep submicron SoC. With the development of production technology, the integration of IC is also continuously improved. The highly integrated circuit faces lots of problems during testing. Due to the ever increasing transistor count and circuit density of modern VLSI circuit, comprehensive testing of such devices meets mange challenges. There are three serious problems: These are test application time, test data volume, and test power consumption. The test application time and test data volume are directly related to the cost of testing. The switching activity and power consumption of serial-scan testing is known to be much higher than normal operation. The excessive heat dissipation caused by high power consumption can produce incorrect responses even for circuits with no actual defects. Further, the overwhelming heat dissipation can damage the circuit under test, resulting in yield loss.Low power test of SoC is researched in this dissertation. Test power can be divided into two categories by its produced forms, one is dynamic power and the other is static power. This dissertation is focus on how to cut down the dynamic test power. As the random access scan (RAS) architectures is useful in reduce test power, the research is based on RAS structure.A new test scheme based on RAS structure is proposed in this dissertation. Firstly several folding test sets are generated to detect most of the faults. Then the test patterns for the remained faults are created by modify test date in scan cells. Test volume is reduced by coding control information of folding sets. The relativity of test patterns is increased by reordering the patterns in folding set so the test power is decreased. Test time is cut down through parallel test pattern loading.Input reduction is used to group the scan cells restrictively so as to reduce the complexity of RAS structure. After grouping, scan cells in the same group share one control signal so the complexity of address counter in RAS structure is reduced. Grouping the scan cells narrow the scope of address which enhance the efficiency of test data encoding. Grouping the scan cells restrictively result in few patterns in folding set so the test time is decreased. The number of scan cells which changed at the same time is increased, so the test power is increased slightly.