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Test Design Of NoC Communication Structure

Posted on:2009-09-05Degree:MasterType:Thesis
Country:ChinaCandidate:S C HeFull Text:PDF
GTID:2178360245968636Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Testing is a necessary part of the IC design process. Due to the continuous increase in the complexity of IC design and process, design for test(DFT) technology is being more and more diffcult as well as important. And system-on-chip(SoC), which embraced various reused IP cores, makes the testing even more prominent. Now the chip design has developed SoC into NoC which is the communicating of multiple SoC. There are large number of transistors and more complex functions in a single chip. In addition under the pressure of market, we must decrease the design period and use a mass of IP cores in design. So NoC architecture has characteristics of large scale and complexity of communication. But the faults during manufacturing become more difficult to test in large scale architecture.We must research advanced test measure, that is using feasible measure and structure in the testing of NoC to reduce the cost of testing. Thus it is significant to research the test measure and the structure of NoC and even future circuits.In this paper, the conception of DFT is displayed firstly and some conventional test methods are showed.The test of NoC communication structure is divided into two parts: the test of inter-switch links, and test of switchs. We use the MAF model and BIST method to test the inter-switch links. The TDG unit and TED unit are designed, simulated and synthesized in this paper. Because datas are transmitted in the form of packets, we can test the switchs with the test packets composed of test datas. This paper proposes two different strategies for implementing the test: sequential test strategy and multicast test strategy. Then we analyze the test time of two strategys.A kind of two clocks asynchronous FIFO is designed, which is used to resolve the metastability with communication between different clock regions. This paper insets a scan chain and isolates the dual ports memory, and designs the test structure. The result shows that the area and power of the circuit exhibits a little increase.Finally, the paper looks forward to the NoC test technology.
Keywords/Search Tags:DFT, NoC communicate structure, test circuit, asynchronous FIFO
PDF Full Text Request
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