The Design And Implementation Of The Multiplication Algorithm With Asynchronous Circuit

With the continuous development of integrated circuits,the area of processor chips is shrinking and the scale of integration is increasing.What's more,the operation and analysis of large amounts of data are increasingly frequent,the structure and operation efficiency of digital processors are required to reach higher standards.At present,the implementation of mainstream processors is mainly based on the synchronous clock circuits design.When the scale of integrated circuits become more and more larger,lots of problems are gradually exposed,such as clock skew,excessive power consumption and so on.However,the asynchronous circuit has the natural advantage of low power consumption,so that the design methodology of asynchronous circuit has gradually become a hot spot.This thesis proposes a method on asynchronous circuits design to solve this problem.According to the principle of asynchronous circuit and handshake mechanism,in this thesis,we will introduce three popular asynchronous controllers,namely CElement,GASP and Click.This thesis will use the control circuit with the Click based asynchronous micro pipeline which obeys a two-phase handshake protocol with “bounded bundle data”.Then for further study and analyze of the multiplication,we should understand the 4-2 compression algorithm and addition algorithm.Furthermore,the overall operation efficiency can be improved to a great extent by improving the Booth algorithm reasonably.Additionally,this thesis mainly introduces a variety of fixed-point multipliers.We propose an extended Booth algorithm,which is different from the traditional one,with the strategy of keeping all the partial products during shifting,then compressing and finally summing.This asynchronous Booth multiplier operates more than 12 times faster than the synchronous one while remaining the area and power almost same.In addition to this,the 24-bit multiplier focuses on the DSP48E1 structure,while the 64-bit multiplier uses the loop structure,so that it can reduce the area of the whole design.Finally,this thesis also emphasis on the single-precision floating-point multiplier based on IEEE-754 standard,which adopts a novel asynchronous for-loop structure.This structure can not only improve the utilization rate of the functional modules,but also reduce the design complexity.The floating-point multiplier is able to run at a time of 30 ns by the synthesis,implementation and simulation.And this new one would reduce the coupling of each function and then simplifying the control part of the circuit.