| The ability of asynchronous circuits to produce a completion signal after each operation gives rise to its two advantages over traditional circuits. They are increasing in speed and the relative simplicity of self-checking implementation. High performance and high efficiency totally self-checking asynchronous datapath design schemes are discussed in depth in this thesis. This thesis results in the following contributions.; The complexity of testing a latch based asynchronous pipeline depends on the method to detect the stuck-at-pass faults in the event-driven latches. In this new parallel test method a few ad-hoc test points is inserted to solve this problem.; A fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. Comparing with handshake architecture of Williams', the new handshake cell is faster due to its protocol which allows precharge signal be removed before the arrival of the valid data from the previous stage. Comparing with handshake architecture of Matsubara's, although both protocols allow precharge signal be removed before the arrival of the valid data from the last stage, the new handshake cell is faster due to its simplicity. And more importantly, the new handshake protocol is robust because it has no timing assumption, while Matsubara's pipeline has to satisfy the precharge width requirement.; It is the first time to associate a totally self-checking (TSC) asynchronous datapath with proven theory. In this thesis, we demonstrate that the asynchronous datapath scheme based on DCVSL circuit belongs to a kind of asynchronous circuit called indicatable two-phase combinational circuit that is TSC under stuck-at-fault model.; The proposed totally self-checking and self-timed (TSC&ST) asynchronous datapath scheme is verified by an 8-bit TSC&ST divider which is implemented by using AMS 0.6 mu m CMOS technology, and the chip size is about 1.66mm x 1.70mm. The chip test results show that: The divider functions correctly and the latency for 8-bit quotient-digit generation is 17ns (about 58.8 MHz). |
