The Verification Of DMC Base On SPECMAN E

As the average gate count for designs now approaches or exceeds one million, functional verification has become the main bottleneck in the design process. Design teams spend 50% to 70% of their time verifying designs rather than creating new ones. As designs grow more complex, the verification problems increase exponentially when a design doubles in size, the verification effort can easily quadruple.Though spend so much resource and time, but there have so many corners have not been cover, that result in the failure of the chip production. So a new functional verification methodology based on generation of constraint-random testbench is presented in industry. The methodology of functional verification can randomly generate the data with limited some constraints.We use the verification platform of SPECMAN-E to verify the DMC (Dynamic memory Controller), and research the new methodology base on the process of functional verification.There have described the flow of verification with E language and Verilog language in this paper. First of all, we wrote the verification plan base on the specification of design, include function coverage, source code coverage require and drawn the environment. We write the environment code with E language and Verilog HDL After completed the verification plan, and regenerated the stimulant and restrict. Last of all, we use the SPECMAN_E and NC_Verilog run the simulation and verification, debug the bug that found by SPEMCNA_E, collect the function coverage and source code coverage. The last of this paper have summarized the advantage of SPECMAN_E and described the prospect of verification methodology.