Specman Elite Based Platform For Automatic Functional Verification

With the progress of the semiconductor technology, the scale of Integrated Circuit design increases greatly. The more complicated the design is, the more risk hides in it, therefore much more effort of verification costs. One problem is how to ensure the correctness of complicated designs. The other is how to reduce the huge verification workload because of verification occupies 50-80% of the whole design process. It is difficult to complete the functional verification of a SoC(System-On-a-Chip) which is in the scale of more than 1 million gates with traditional verification method.The paper provides a solution of reusable automatic functional verification platform according to the characters of SoC, then using the platform to complete verification of CEU(Configurable-Encryption-Unit) module. The verification platform is based on E language, one of high level verification languages. The application of E language as a kind of high level verification language makes the functional verification more efficiency, especially in building a verification platform. In accord with the rules of reusable methodology manual, the platform could verify the modules in SoC chip automatically. As for the reusability of the platform, different modules could be verified through specific configurations respectively. Therefore the work of verification is reduced and the efficiency is improved.