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Research On Functional-Information-based Verification Engineering And Verification Techniques

Posted on:2006-01-15Degree:DoctorType:Dissertation
Country:ChinaCandidate:D L ZhangFull Text:PDF
GTID:1118360152490182Subject:Precision instruments and machinery
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With the booming of the scale and complexity of IC design, the reuse-based SoC design methodology has become a predominant paradigm in IC design industry today. Functional verification has become the bottle-neck of the upgrade of design efficiency. The solution lie not only on the breakthrough of the technique or method, and also on the efficiently management and organization of the whole resource of the industry. Researches on the functional verification engineering are meeting an inevitable demand as the gap between efficiency of SoC design and that of functional verification is enlarging. The Functional-Information-based Verification Engineering(FIVE) has been proposed in this dissertation. Topics in the dissertation are emphasized on system structure and process of the verification engineering. And several support techniques are involved in detail under the framework of FIVE.This dissertation is supported by the following projects: the project of 'Study on the Platform-based Methodology and the Key Technique of SoC design'(NO. 60373076) supported by the National Foundation of Science of PRC, the project of 'Study on the Theory and Method on Hardware/Software Co-design and verification optimization'(NO. MOE [2001] 215) supported by the National Foundation for the PRC Ministry of Education. The main work and achievement are as follows:1. The basic methodology and the development trend of the functional verification are analyzed. Then the orientation rule of the development of functional verification is studied and demonstrated theoretically.The concept of the Verification Engineering is proposed in the dissertation. By introducing the concept of the functional information, the Functional-Information-based Verification Engineering is proposed to achieve a universal scheme for the functional verification.A process model of FIVE is set up and the basic elements, including the generation and application of the functional information, the research on the theory, tools and methods, the formalization and standardization, are discussed. At last, a model for the evolutionary process from the current verification methodology to FIVE is involved.2. Under the direction of FIVE, the template-based automatic generation of verification stimuli is involved. The synthesis method of instruction template is introduced, which separates the description and the implementation of template into two orthogonal parts. As a result, the orthogonality reduces the complexity of the template describing and improves the reusability of the template description.From the perspective of instruction coding, a three-level description method is put forward. The three levels are the format level, the content level and the constraint level, respectively. The orthogonality of the three levels increases the usability and scalability of the template.Base on the template, the method of the test code generation is discussed. A Branch Switch method by 'token transfer' is proposed, which makes branch instructions being able to be randomly loaded into a test code train without incurring a infinite-loop. The process of the instruction generation is optimized with the selfish gene algorithm. A C-model coverage metric is introduced, which speeds up the optimization process greatly.3. The method of assertion-based automatic generation of monitors is involved. Based on the traditional definition of assertion, a sub set of assertions is constructed, which balances efficientlybetween the description ability of Property Specification Language (PSL) and the simplicity of the 'Stanford assertion'. A formal definition of assertion is defined.The process of monitor generation is divided into two parts. First, the assertion description is transformed into a sequence of events. And, the formula model of the transformation is presented. Secondly, monitor is generated based on the sequence of events. Two methods are put forward to be as solutions. One is base on synchro-postponing the events into the same cycle, the other is based on the finite state machine construction. A the...
Keywords/Search Tags:functional verification, functional information, verification engineering, process model, instruction template, stimulus generation, monitor, assertion, verification model, frequency multiplier
PDF Full Text Request
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