NoC Functional Verification Based On Specman-E

As the scale of integrated circuit design is bigger and bigger,and the function is more and more complex,functional verification has become a bottleneck in the process of integrated circuit design,which occupies 70% of the time the whole design cycle.The traditional verification method based on Verilog HDL or C language has been unable to meet the verification demand of the current chip system of VLSI.Build verification platform based on Specman-E and EVC,combine the automation tools and validation platform,which has good extensibility and reusability,can meet the validation needs of current complex system.This thesis based on automated verification platform which designed with Specman-E,mainly consists of three parts,one is the validation component named bus EVC,the second is the validation component named So C_EVC,It realize the configurational using of EVC bus on the top floor,and the environment configuration of the on-chip network's various peripherals and total line bridge,the third is the the scoreboard which is port to port and design for features of the on-chip web,namely port2 port scoreboard,to deal with and check the data of initiator and target port,to ensure the validity check of the internal transfer data of NOC.Based on the verification platform,this thesis has carried out sufficient validation on the basic function of on-chip network,including basic communication on connectivity of network,security of firewall security,address assignment of target port and selection of hready signal under the condition of multiple ports,configurational function of power of initiator and target ports,accession on protected address of memory,and so on.Because the No C connected to more than 40 unused IP module,for data transmission requirements of each different IP module,need to generate the corresponding random testing incentives,such as for IP module of AXI interface,you need to do data flow testing of out-of-order and significant transmission,etc.Through the effective constraint of the data's test scope,access to the situation of the horn side which is difficult to consider,to found some problems which hidden in the design as much as possible.Building the verification platform based on this thesis has found a lot of design errors as early as possible,including errors related to firewall security,configuration errors of bus properties,processing errors of data instruction,errors of address allocation,errors of acrossing address boundary,configuration errors of NIU attribute,configurational behavior errors of the power and so on 26 design errors,after communication with designers,successfully solve these design errors,avoid to pay a huge price if find the similar mistake late in the project.Finally in this thesis the verification platform has done a lot of regression testing on all effective test incentive,the simulation has run a total of 952 random seeds,finally the result all passed.The global code coverage reached 98.67%,the lines of code coverage,flip coverage,branch coverage were more than 97%,achieved the desired validation index,functional coverage has reached 100%,ensure the all cover of the function points,the test data instructions that the final validation quality of Network on Chip which based on this verification platform is at a very high level from the front.And because of this verification platform has good extensibility and reusability,it can be easily reused for new projects,and also has a great significance for the follow-up project.