Research And Development Of A Bus Verification Component On A SoC Using Specman Elite Platform

With the increase of the complexity of SoC (System on a Chip), the workload of functional verification has increased expeditiously. It is difficult to complete the functional verification of a SoC which is in the scale of more than 1 million gates. The application of e language as a kind of HVLs (High-level Verification Languages) makes the functional verification more efficiency, especially in building a verification platform. To further enhance the efficiency of verification, the e language based commercial verification components (eVCs) become popular in the IC industry. Because of their plug-in style, eVCs help verification engineers to complete verification platform with high efficiency. However, such commercial eVCs almost focus on the general SoC architectures or protocols. Engineers always feel hard to choose eVCs for a SoC project which relates to creative architectures or protocols. The commercial eVCs don't support the creativity in new architectures and protocols. This is not conducive to the diversified development of SoC technology.In view of the shortcomings of commercial eVCs, this paper presents a development method for the Verification Component using e language, and achieves a reusable, configurable structure in the verification component. The SS06 bus verification component has been developed during the work of this paper, and several related verification platforms have been built. The applications of the verification platforms prove the practicality of the development method.