With the rapid development of wireless communication technology and CMOStechnology, research of fully integrated radio frequency (RF) transceivers has beenhighly promoted. Among advances in these researches, high-performance frequencysynthesizer is the key to the overall performance of integrated RF transceivers.In this thesis, the architecture and linear model of charge pump phase-locked loopare introduced. Meanwhile, the principles of operation, basic circuit configuration andperformance parameters of voltage-controlled oscillator in the phase-locked loop arealso researched. Simultaneously, the phase noise of the oscillator is analyzed accordingto the mathematical model of the phase noise, and the advantages and disadvantages ofdual-modulus prescaler are compared between traditional dual-modulus prescaler andthe phase switching technique-based prescaler.According to the requirements of2.4GHz wireless transceiver for Zigbeeapplications, a LC voltage controlled oscillator and a fractional dual-modules presaclerare designed using TSMC0.18μm RFCMOS technology. Voltage controlled oscillatoradopts differential complementary cross-coupled pairs and binary varactors arraies, toachieve multi-channel frequency tuning, as well as to improve output swings and tooptimize phase noise. Moreover, automatic-amplitude control circuit is used to stabilizethe output amplitude. The dual-modulus prescaler adopts phase-switching architecture,and the divide-by-2dividers adopt current model logic architecture to improve thecircuit operating speed and lower power consumption. The circuit is simulated bySpectreRF, and the results shows that frequency of LC voltage-controlled oscillator is4654-5172MHz, center frequency of which is approximately4.87GHz; the tuning rangeis up to37.2%; the power consumption of core oscillator is about0.74-2.75mW; thephase noise of center frequency is-91.34dBc/Hz@100KHz. The division ratio ofdual-modulus prescaler is32/32.5, with highest operating frequency up to7GHz,consuming a2.83mW-power, and the rising/falling delay of output signal is91.6ps and95.9ps, respectively. The simulation results show that the design meets the specificationof the system. |