1Mb High Speed Low Power SRAM Design

The big bit-line capacitance is a main bottleneck for high speed cache on a chip. In this thesis, a hierarchical divided bit-line (HDBL) approach is used for reducing active power in SRAMs by reducing bit-line capacitance. This division of bit-line into hierarchical sub bit-lines results in reduction of bit-line capacitance, which reduces active power and access time. The method of hierarchy division in literature is modified to obtain optimum values. Also the equations of active power and access time are derived and modified. Experimental results show that the observed parameters are accordance with the estimated values. It is shown that the reduction in bit-line capacitance reduces active power consumption and the access time and there is only the expense of approximately 4.1% increased in the number of transistors.With the constraint in the sizes of transistors in reading and writing operation of HDBL SRAM cell and derived the SNM expression and simulation, the transistor sizes in HDBL SRAM cell are obtained. The results indicate that the HDBL SRAM cell have a more stability than usual six transistors SRAM cell.By dividing the HDBL SRAM matrix into eight blocks and making memory matrix reasonable placement lower power consumption is achieved. In the design of periphery circuit , block decode circuit, predecode circuit and hierarchical decode circuit are used to improve the operational speed and lower consumption. By referring the current sense amplifier (CSA) scheme proposed in a literature a high sensing operational speed and active power consumption is developed. The speed of row decode circuit is 1.48ns. Both the speed of block decode and column decode is 0.27ns.The speed of CSA is 0.29ns in 10MHz. The maximal active power consumption of HDBL SRAM in reading operation approximately 90.69% of that in usual SRAM . And the active power consumption in writing operation approximately 75.31% of that in usual SRAM.