Design And Realization Of High-speed And Low-power SRAM

With the rapid development of microelectronics, SRAM are getting more and more high-integration,high-speed and low-power. Moreover, semiconductor memories have been the cornerstone of the whole information age. In the recent years, SRAM has played the positive role in the aspect of improving the capability and reliability of the chip and reducing cost and power. In this paper, the design of hign-speed and low-power is expatiated particularly. Firstly, application and development of semiconductor at home and abroad, the structure and work principle of SRAM are discussed. Then, memory cell array and some parts of peripheral circuits used in SRAM, for example, sense amplifier and pulse generator circuit are designed in the design. Cross Talk in Memory Array was brought about ,thus interval decoding architecture and alternate decoding architecture were applied in the design, which not only reduce cross talk among memory cells, but also improve the reliability. The architecture of DWL can decrease the power. The characteristic of delay on word-lines was improved by adopting decoding architecture. By ameliorating the architecture of Sense Amplifier, the access time was abridged. In mask design, the way of TOP-DOWN and DOWN-TOP was applied , layout was programmed logically.