Design And Optimization Of S Unit Of A 600MHz DSP Chip

Digital Signal Processor (DSP) is a kind of processor made specially for digital signal processing. DSP technology developed rapidly since the first DSP chip produced in 1980s. Nowadays, DSP is widely used in many fields, especially in communication technology, military application, and control system. Higher performance DSP is required for new applications.FT-CXX is a 32-bit fixed-point DSP chip being designed. Its architecture is VLIW and it can issue 8 instructions in a cycle. It is bound to run at a frequency of 600MHz, which would be the DSP with the highest frequency we have ever designed. I am honored to be a member of the reserch team to take part in the design of S Unit which is one of the most important function unit in CPU core. In this paper we will describe the architecture of the S Unit in FT-CXX, the logic design, as well as the optimization of crucial parts in the design by use of full custom design method to achieve the goal of 600-MHz frequence.S Unit is an important function unit carrying on logic operations, arithmetic operations, and branch instructions in FT-CXX. In this paper, we will start with analyze of the architecture of the S Unit, and divided it into small segments according to instructions. Then we elaborate on the logic design of S Unit, and make an evaluation of its performance. An timing barget was made for the crucial part according to the design objective.Barrel Shifter is a main functional unit in S Unit and is surposed to be the bottleneck considering that there is a instruction taking two shift operation in one clock cycle. We have done some experiments to find that the problem can't be solved unless we design the shifter with the help of full custom design method. By using dynamic circuit technology, We have succeeded in finishing a Barrel Shifter layout with a data latency less than 300ps and an area of 70um×70um, which is perfectly reach the goal.As proved that dynamic circuit is good for its high performance, and it is also known for its small noise margin and bad signal stability. So some improvement for dynamic circuit is discussed, mainly on performances and noise-immunity. The performance has been improved by more than 25% with the help of footless dynamic circuit design, Dual-Vt CMOS technology and skewed CMOS design method. We analyzed the noise sources and did some experiments to compare some kinds of noise-tolerant technology and use them to improve noise-immunity of the shifter. Also an evaluation has been made to ensure the shifter can work correctly with the interference coming outside.After one years' study we have finished the logic design and full-custom optimizations of S fuctional Unit, and performance bottlenecks have been solved.