Full Custom Design Optimization Of YHFT-DSP's ALU Unit

Operation unit as an important part of datapaths, is the core of DSP, has great influence on chip's performance, area and power consumption. The aim of this dissertation is to discuss how to optimize the operation units.Due to the process of L unit's pointing and floating operation in "YHFT"-DSP, full-custom designing method is introduced to optimize the design of ALU units. The optimization parts are composed of the first stage's 41-bit adder, the second stage's 56-bit shifter and the third stage's 56-bit shifter.In the design of adder, base on the studying of many fast adder, we adopt K-S tree which is the most fast adder algorithm. After the logic design and layout design, simulate the R/C extraction data with Hspice. In the typical condition, the longest delay is 0.955ns, the area is 12280μm~2.In the design of barrel shifter, comparing with kinds of decode and shifte structure, we take the 2 stage hybrid-decoding method that has fast speed and good stabilization. Nmos-only shifter array can reduce power consumption saliently. Simulate the R/C extraction data with Hspice. In the typical condition, the longest delay(from decode to out) is 0.734ns, the area is 8152μm~2.An entire test process after manufacturing has been discussed in the dissertation. Depending up on FPGA, we could easily test the chip's function and capability(speed) with scan test method. Furthermore, we set the view of full-custom module. Then, embed them in the whole semi-custom design flow from synthesis to detailed route. As a result, the three stages have about 0.3ns's improvement in timing. It is clear that the combination of full-custom and semi-custom design is more excellent in performance, area and power consumption than pure semi-custom design.