A Full Custom Design Of Critical Units In The Pipeline Of FMAC

The structure of floating-point Multiply-Add-Fused (MAF) is so complex, that its latency of logical-implement is very long. It's a main bottleneck of the design of high performance processors. So to improve the performance of processors is very important to implement the MAF with faster and better ways. The traditional half custom way to implement the MAF can not catch up with the development of high frequency of the processor yet. Since that, based on the half custom design, using full custom way to design some necessary Arithmetic logic unit on circuit's critical path, is a very effective method on this problem.This thesis emphasizes on how to design some logic unit on critical path in full custom way. It represents the design of two different high performance Shifters in 0.13 CMOS process, and optimizes them at algorithm level, circuit level and layout level. This thesis mainly contributes to the following aspect:On the aspect of half custom design, using a new three-operand Leading-Zero-Anticipate(LZA) algorithm, improves the performance of LZA unit which has long lantency.And it is proved to achieve a good balance between speed and area.Design the 162-bit Shifter on the normalization path of the MAF and the 54-bit shifter on the non-normalization path with full custom design.Using FO method and Logical Effort method analyses the load of circuit,and confirm the size of transistors.Based on that,using STA do a further and exact optimization.This practice have better effect.In slow case,the delay of critical path of two shifters are 0.75ns and 0.55ns,average power disspation are 19.986mW and 0.916mW,and layout area are 0.03392mm~2 and 0.00557 mm~2.This designs achieve the goal of higher speed,lower power dissipation and smaller area.