The Full-Customed Design And Optimization Of Arithmetic Unit On High Performance DSP

This is an information society and a digital era. With the development of information technology and computer technology, digital signal processing technology has shown its increasing importance in every domain. The key technique in digital signal processing technology is digital signal processor (DSP), which carries increasing demand on its performance. Arithmetic unit as the core of DSP has great influence on chip's performance, area and power consumption. The aim of this dissertation is to discuss how to optimize the arithmetic units.In this dissertation reviewed the history of the DSP techniques, analyzes the technology characteristics and developing trends of DSP, and follows the technique characteristics of arithmetic unit in high-performance DSP chips. As a result, a full-custom designing method is introduced to optimize the design of arithmetic units in YHFT-D4. The full-customed Barrel shifter with decoders, adder and multiplier has advantages, in sequence, chip area and power consumption over shifters, adder and multiplier designed using stand cell synthesis methods.Full-decoder circuit structure is used in Barrel Shifter design. The area of full-customed Barrel Shifter is only 90* 135sq.μm.. Spice simulation shows that the frequency of shifter input data can reach 1GHz in worst case circumtance.Operation speed of adders has ultimate effect on the speed of processors. Advanced Hybrid Prefix Adder Han Carlson structure is adopted in adder design which is a find trade-off between logic level and fan-out. The domino dynamic circuits adopted in the adder have a speed of 1.5 to 2 times faster than static circuits. However, dynamic circuit always brings about problems such as coupling capacitance, charge sharing and so on. Measures to solve or prevent these problems are presented in this dissertation too.Performance of multiply operation is an important factor in evaluating DSP's performance. In the multiplier designing, we adopted various advanced modern multiplier design techniques. This multiplier has two working modes, normal mode and SIMD mode which support 16-bit multiplication or two 8-bit multiplications respectively. In partial product generation, we adopted limited sign extension technique which reduces the length of partial product. 4-2 tree structure is used in multiplication array design. This is a quick and tidy design. Transmission gate circuit used in 4-2 adders greatly reduced transistor quantity while increased system speeds in the meantime.Enterprise EDA tools of Synopsys Company are used in layout design. Top-down method is used first in global designing stage, and then bottom-up method is used in layout design. Latch up prevention measures are taken in order to ensure reliability of the layouts.Finally, this dissertation discusses how to embed full custom design into synthesis-based procedure and hardcore IP encapsulation. Index selection in Synopsys view look-up table of full custom design is carefully solved here.