Design And Optimization Of 600MHz Branch ALU Of YHFT-DX

YHFT-DX is a fix-point DSP with the VLIW architecture developed by National University of Defense Technology, which can execute up to 8 instructions per cycle and can work at the frequency of 600MHz. Branch arithmetic logic unit (BALU) is an arithmetic logic unit (ALU) with the branch control function. The operations of BALU are very complex making BALU the critical unit of YHFT-DX. So there is scientific researching and engineering significance to research the design of BALU.This article researches the full-custom design and optimization of BALU, and completes the entire circuit and layout design using the 0.13um CMOS technics. The simulation turns out that the longest post-layout delay of branch control unit is within 1.2 ns. The main contributions are as follows.1) The position of BALU in the pipeline is introduced, and the design aims of decode stage and execution stage are analyzed respectively. Then, the decode stage is realized with RTL, and the outcome of post-synthesis is 0.95 ns.2) The function of execution stage of BALU is introduced modulely and the critical path of every module is analyzed. Based on this, the operations which limit the speed and the size of each module are researched and optimized. With the method of structure modification, the control race of the result-selection logic is settled; by means of the arithmetic optimization, a forty-bits shifter with two stages and asymmetric decode is designed; with the enhancement of parallelism, the critical path of SIMD is optimized; via the way of dealing in terms of byte, the size of bit operation module is reduced.3) Adder is vital to processor design. This article introduces one 32-bit adder, which uses new-style FCSL algorithm. Optimization is introduced to the FCSL adder with the method of limited dynamic thought. The result shows that the post-layout delay is 410ps.4) Routing channel method of layout design is raised which reduces the complexity in the layout design. And the executation stage of BALU is completed in this way. Moreover, the factor which affects the reliability of layout is analyzed.5) Hybrid verifications of both RTL code in decode stage and executation stage circuit are made, in which, the method of transition from circuit to Verilog model is introduced. And then, the former simulation and latter simulation is completed.6) Test chip design is presented. In this design, serial scan method is adopted to test the function as well as the performance of the data path made up of BALU and register file. The pre-silicone outcome shows that the data path can work well at the frequency of 600MHz.