The Research And Design Of 32bit Scalar Micro-processor In Video DSP XY-VDSP

This thesis is originated from a national 863 Project, the Design of Video DSP Core. It focuses on the research and design of scalar processor of Video DSP XY-VDSP.The thesis describes the design and implementation of 32bit scalar micro-processor in XY-VDSP Video DSP with top-down design methodology. The FPGA prototype is also verified successfully.According to the research plan, the major work fulfilled by the author is follows:Firstly, the author of this thesis participates in studying and designing of the architecture of the Video DSP. Then the author investigates and presents the design scheme of the 32bit scalar micro-processor, and performs complete circuit design of the whole 32bit scalar micro-processor. Especially, this thesis studies the implementation of adder and shifter, which are the two key components in the data path under researching, and implements carry skip adder and barrel shifter in the 32bit scalar processor.Secondly, this thesis discusses the design scheme of the interruption controller and built-in debug aides, and implements their functions.Thirdly, the task of this thesis goes through the function simulation of the whole scalar micro-processor, including single instruction simulation, special instruction program segment simulation and application program simulation. And furthermore, the function simulation of the whole scalar micro-processor is completed in the environment of video DSP.Finally, the whole 32bit scalar micro-processor has verified using FPGA prototyping.This research work has been checked and accepted by the expert group of National 863 Project successfully. The research results of the thesis will be beneficial to the design process of the self-developed Video DSP processor of our own nation, and will have significant applications in the future.