Design An Analog Front-end For Pipelined ADC Without A Sample-and-hold Amplifier

The traditional A/D converter contains a sample and hold circuit, the disadvantageof the sample-and-hold circuitis is more than30%of the power consumption of thatentire A/D converter is consumed, in case of the high precision and high sampling rate.This thesis is based on ensuring the pipelined A/D converter system performance not todrop, the sample and hold circuit of the pipelined A/D converter is removed to achievethe purpose of low power consumption.This thesis describes the importance of the front end circuit for a pipelined A/Dconverter, and the performance of front end of the sample and hold circuit determinesthe system performance of the entire pipeline A/D converter, so it must spend morepower consumption to ensure that properties of the front-end sample-and-hold circuit.This topic solution is that by removing the sample-and-hold amplifier analog front-endstructure, the entire pipeline A/D converter achieves low-power design requirements.The analog front-end circuit includs Sub-ADC module circuit and MDAC modulecircuit.This paper describes the impact of the Sub-ADC and the MDAC unit circuit inthe whole pipelined A/D converter system after removing sampling and holdcircuit,and obtains the request of the pipelined A/D converter without sampling theanalog front end circuit of the amplifier, and analyzes the cause of the delay caused bythe front end circuit，and propose a matching technology of front-end Sub-ADC andfront-end MDAC.Then, this paper decribes a designation of sample-and-hold amplifieranalog front-end circuit, including a high-performance of the residuals amplifier, thehigh-speed, high-speed bootstrap switch, high-precision MDAC, randomized design ofcomparator array. And by reasonable territory placement and routing, reduce pathparasitic impact of the the analog front-end, and solve the problems of the processing ofthe analog input of the Sub-ADC and MDAC at the same time.The design of this project is based on the the precision of14-bit pipelined A/Dconverter, the sampling rate of200MSPS, the design process using a0.18μm standardCMOS process, the power supply voltage of1.8V. The analog input frequency of theentire pipeline A/D converters is in70MHz, and the sampling rate of200MSPS， the SNR of the pipelined A/D converter is71.7dB, SFDR is78.1dB. The powerconsumption is less than300mW. This project effectively reduce the system powerconsumption,by removing analog front-end circuit of a sample-and-hold amplifier,andensure the performance of the high-speed and high-precision A/D converter.