Design Of 12-bit SAR ADC Based On Low Voltage And High Precision

With high-speed development of microelectronic technology, especially the increasing use of digital computing and signal processing technology in applications, it is becoming common to deal with analog signal with digital circuits. So digitalizing analog signal is the trend of information technology, in which Analog to Digital converter plays an important role. Successive approximation (SAR) A/D converters are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 Mega samples per second (Msps). Because of providing low power consumption as well as a small form factor, SAR A/D converters have a wide variety of applications, such as portable/battery-powered instrument, pen digitizers, industrial controls and data/signal acquisition.In this paper, a 12-bit low power SAR A/D converter with medium speed is designed, which can work under a 1.8V power supply. This paper mainly focuses on several parts: S/H circuit, D/A converters, capacitance array and digital logic control in time sequence. Other group member completed the design of comparator.This design uses the difference technique and bottom sampling technique to overcome the charge injection effect and the clock feed-through effect. Improve the A/D converter accuracy at the same time, sampling capacitor embeds into the D/A converter capacitor array, takes the expansion of parallel structure to ensure the accuracy of conversion effectively and save the chip area. In the design of the capacitor array, it uses the unit's method to reduce the mismatch error of the parallel MIM capacitance value, and adopts a whole concentric layout to increase conversion accuracy. In the digital control module of the circuit, design the successive approximation logic which based on the ring counter/shift register. In the overall layout design uses Mixed-signal (AMS) design flow, that is, in the design of digital part, uses the Full-Custom Design methodology based on the standard cell. In the analog part, uses the Full-Custom Design methodology, so as to shorten the design cycle and improve the performance and silicon available area.In the design, the SAR A/D converter is based on IBM 0.18um DP6M CMOS7RF mixed-signal design process, which uses the MPW (Multi-Project Wafer) to tape out by MOSIS. So in the same layout, there are also 8 - bit CPU design and low noise charge pump 100 MHz PLL Synthesizer Design. The layout area of the SAR ADC is , the MPW area is . After the completion of the layout on the whole circuit simulation, the simulation results show that the design meets 12 A/D converter requirements, the SAR A/D converter can work well.