Low-power Mixed Analog-digital Integration Technology Research And Design Examples

The topic of this thesis is low power mixed-signal design technique. It includes the analysis of basic principles of this technique and these theories are applied to three design examples:discrete-timeΣΔADC, continuous-timeΣΔmodulator and FPMA (Field Programmable Mixed-signal Array).With the development of IC design, low power design and SoC design become the two main topics. The concept of green electronics, popularization of portable products and increasingly lack of energy make low power design the most important target of modern IC design. The SoC design method integrates analog signal processing modules and digital signal processing systems together so as to minimize die area, extend single chip function, increase operating frequency and cut chip cost. Under this background, this thesis summarizes many low power mixed-signal design techniques and makes further analysis.As a combination of analog modulator and digital filter,ΣΔADC is a typical mixed-signal system. Applications such as stereo CD, DVD audio and high performance power meter need ADC with bandwidth up to 100 kHz and 16-bits resolution. For this application, a discrete-timeΣΔADC is designed with 1st order 2nd stage structure and single-bit quantization, and chopper-stabilization method is used in the first OP AMP to minimize flicker noise and mismatch effect, sub-threshold design technique is used in the input stage of OPAMP to get a larger gain and bandwidth under specific power consumption. Test results show that analog modulator consumes 9.8mW and digital filter consumes 5.7mW, dynamic range reaches 92dB in the 96 kHz bandwidth.The widely used third generation communication wireless systems, multi-mode cellular transceiver handset and many communication standards demand ADCs with several MHz bandwidth and 14-bit or better resolution, which beyond the traditional discrete-timeΣΔADC capability. During recent years, continuous-timeΣΔADC has become a feasible and suitable ADC approach for bandwidth of higher than 1MHz due to low power consumption, wide bandwidth and small area with respect to its discrete-time counterpart. However, continuous-timeΣΔmodulator suffers a lot from clock jitter because of their higher sensitivity than discrete-time counterpart. Moreover, coefficients of continuous-timeΣΔmodulator such as RC time constant in active-RC integrator have a large variation which can reach±30% because of temperature and process variations. A novel clock jitter error compensation and auto-tuning structure is proposed in this thesis to improve ADC performance under these non-ideal conditions. This structure is implemented in a third-order single-bit modulator operating at sampling frequency of 200 MHz and OSR=48. Compared with modulator without compensation, the SNR is simulated to be improved by 30 dB under a clock jitter of±2.5%. The coefficients of modulator are simulated to be tuned to the value with the error of less than±2.8% under the process variation of±30%.The mainstream of present data processing method is in digital way with realizations in DSP and FPGA. As a result, ADC is needed as input interface and DAC is needed as output interface when processing analog signals, which increases design complexity and consumes extra power and area. In order to save power while maintain performance, an FPMA is designed in this thesis, which includes field programmable analog array (FPAA), FPGA, MCU, SPI interface and clock generator. Test results show the FPMA chip could realize many complex analog, digital and mixed-signal operations with lower power than similar devices in the market.