Research On Key Technologies Of Mapping And Router In Network-on-Chip

With the number of integrated IP cores increasing in current System-on-Chip (SoC), limited by scalability and bandwidth in practical application, traditional bus or multi-layer bus cannot meet the needs of communications between IP cores. As the most promising alternative technique, Network-on-Chip (NoC) communication architecture has emerged to address the problems which the traditional on-chip bus has been faced with. NoC uses micro-network for inter-IP communications by packet. However, different from the macro-network, NoC puts forward a series of new challenges, including constraints in power, area and communication latency.This dissertation makes an attempt to touch on the key technical problems related to NoC design. More precisely, the author makes an in-depth study on IP core mapping methodologies, routing algorithms and router architecture. The specific contributions are as follows.1. For NoC design, IP core mapping is one of the effective ways to optimize network performance and energy consumption. In this dissertation, the author improves the ant colony algorithm and makes it possible to solve the low energy consumption mapping problem, which is based on genetic and ant colony (GAAC) mapping algorithm. This algorithm has used heuristic information, which is irrelevant to topological structure, so that it applies to NoC mapping problems of different topological structures. In addition, to prevent this algorithm from getting into premature stagnation, strategies such as crossover of chromosomes and roulette wheel selection have been introduced in GAAC mapping algorithm. The experimental results show that GAAC mapping algorithms could solve NoC mapping problems of different topological structures effectively. Compared with basic ant colony mapping algorithm, when this algorithm is used to solve mapping problem of the3×3,4×4and5×5NoCs, the communication energy can be saved respectively about2.2%,6.3%and8.1%.2. Based on the topology characteristics of3D mesh NoC, the corresponding energy model has been improved. At the same time, a fast and low energy consumption mapping algorithm SYMMAP is proposed based on topology partition. According to the experimental results, when solving3D mesh NoC problems, SYMMAP takes great advantages over the existing heuristic mapping algorithm in terms of mapping speed and energy consumption.3. Different mapping results may have different impacts on NoC metrics such as maximum latency, power, fault robustness, peak temperature etc. Different aspects need to be taken into consideration when optimizing NoC mapping objects. For this problem, this dissertation takes account of both power and temperature problems in NoC mapping, using multi-objective ant colony algorithm (MOACA) to optimize these two NoC metrics. MOACA algorithm can find the pareto-optimal front effectively and keep power and temperature in balance while being optimized. The results show that the mapping scheme by using MOACA can reduce the chip peak temperature as well as the chip power. Different from the mapping scheme while using PBB which is a single-objective power optimization mapping algorithm, the mapping scheme for Multi-Window Display (MWD) based on MOACA can make the peak temperature of chip reduce4℃, while the chip power remains stable.4. Routing algorithm has a great effect on network performance and communications efficiency, so design and implementation of routing algorithm is one of the most critical issues during the NoC design. For the communications characteristics of the3D mesh NoC mapping scheme and the mapped IP core, this dissertation proposes an application-specific routing path allocation method based on channel dependency graph. This method can maximize the adaptivity of routing path under bandwidth constraints. What’s more, the proposed method can guarantee deadlock freedom with no need of any virtual channel. According to the analysis and simulation, the proposed method provides better network performance when compared with other common deadlock-free algorithms.5. The main objective of NoC fault-tolerant technique is to guarantee sustained communications when fault happens. Fault-tolerant routing algorithm is an efficient way to achieve fault tolerance in NoC. In this paper, to solve the problem of different faulty routers in2D mesh NoC, the author proposes a new routing algorithm MFRT with the ability of tolerating different faults. MFRT can tolerate different faulty routers distributions in NoC by reconfiguring routing paths dynamically. From the results of analysis and experiment results, it is clearly shown that MFRT can enhance the reliability of communications and offer considerable fault-tolerant capability. Compared with XY routing algorithm and single fault-tolerant routing algorithm, if the probability of faulty router is10%, MFRT can improve the reliability of on-chip communications by48.3%and9.56%.6. For hardware resource overhead of on-chip buffer is large and the problem of low efficiency, a new on-chip router named PSBR is proposed. The proposed router maximizes the buffer utilization by allowing sharing them. To simplify the control circuits, a partially shared buffer strategy is applied to PSBR design by an analysis of on-chip communications load distribution, and PSBR is achieved based on Verilog HDL. The synthesis and simulation results show that PSBR can save15%of chip area and28.2%of router energy consumption, when compared to the typical on-chip routers under the same communications performance metrics.The research results in this dissertation provide a series of feasible solutions for NoC design and optimization, and they offer theoretical basis and practical experience for further improvements in reliability, scalability and practical performance of NoC.