Research And Implementation Of High Performance Packet Buffers Based On Hierarchy Memory

With the rapid development of Internet link-rate to OC-768(40Gbps), Network nodes must provide a certain degree of QoS control as well as enhance the performance of data process. As a network system of store-process-forward, network processor has to buffer IP packets firstly, and then process them according to IP protocols. Because the arriving rate of IP packet vibrates dramatically, it is requested that the packet buffer should provide large capacity, high bandwidth and fast storage to absorb the data fluctuation.Based on characteristics of common memories, the required performance of a packet buffer memory can hardly be provided by a single kind of memory device. In view of the above features, combined with the hierarchical storage system, this paper proposed a fast packet buffer composed of fast SRAM and slow but large-storage DRAM, which can realize high performance with low cost.The management mechanisms of packet buffer are also provided. The mechanisms have3key components:the packet buffer addresses management, enqueue-dequeue management and forwarding queue scheduling. These management mechanism can reduce the access to DRAM, which will consequently improve the efficiency of packet buffer storage and ensure that every forwarding queue enjoy equal bandwidth.In order to improve data throughput of packet buffer unit, a multi-channel storage scheme is put forward in this thesis. The multi-channel scheme supports any number, even none power of two, of channels and the channel-selection are realized completely by hardware. A3-channel DRAM scheme is adopted by the packet buffer storage. The interleaving among channels can effectively hide the long random access time to DRAM and then increase its actual data bandwidth.The functional simulation of the whole management mechanism of packet buffer unit is completed lastly. And the performance comparison is launched between single-channel and3-channel DRAM scheme of packet buffer unit. As results shows, the data throughput of3-channel scheme is improved by98%than the single-channel one. The performance of packet buffer storage is improved remarkably.