Cluster Interconnection Network Research

The cluster system plays a dominant role in the high-performance computing field for its favorable scalability, usability, reliability and very high performance-to-price ratio. The performance of nodes in the cluster system is increasing continuously, which calls for corresponding improvement on the performance of the interconnection network in the system, in case that the network becomes the bottleneck. Hence, the study on the cluster interconnection network is always a major issue of the high-performance computing system architecture.The grid-oriented architecture of high-performance computers is an important direction for the computer architecture development. The interconnection network in Inter-grid systems should be able of supporting the application-level communication, so as to share the system resource among the clusters. It is of great importance to study the Grid-switch as well as its network structure.Along with the design and implementation of Dawning high-performance cluster interconnection network– UX8, we studied some key technologies on building a large bandwidth, low-latency, scalable cluster interconnection network. Based on the grid-oriented high-performance computer architecture put forward by NCIC (National Research Center for Intelligent Computing Systems), some important properties of Grid switches are studied and a kind of full-interconnected optical network is proposed in the thesis. Main results are as followed:1. By studying the mainstream cluster interconnection networks, we summarized some key technologies in the design and implementation of cluster interconnection networks: the transfer channels of the interconnection networks and the way of the clock synchronization; wormhole routing switching and the flit-based flow control; scalable network topology; simplified link transmission protocol. We also proposed a hierarchical model to define the relationship among these key technologies in the thesis.2. We designed and implemented a simplified link-level protocol with elastic buffered flow-control and buffered wormhole routing switching, it can support to transmit variable-length packet.3. LRSP arbitration policy for link scheduling in the switch chip was also proposed, in which data paths are assigned in packet according to the Least Recent Served Preference (LRSP) policy during the process. The implementation result shows that one scheduling process can be completed in three clock cycles.4. We also proposed a kind of switch chip architecture with dual-channel ports and distributed arbitrators. The dual-channel ports increased the bandwidth and the distributed arbitrators accelerated the scheduling process thus reducing the routing latency. The implementation results of the FPGA-based UX8 chip show that the bandwidth of each dual-...