Research Of Development And Verification Platform For Network-on-Chip

The continuous evolution of semiconductor technology enables billions of transistors to be integrated into a single silicon die. Due to the huge transistor budgets, designers can realize complex multiprocessor SoCs. As semiconductor technology scales into DSM domain, wire delay increases. The clock signal requires several cycles to traverse the chip, and clock skew become unmanageable. Thus, it becomes extremely hard to synchronize a chip with a single clock source. To solve the problem, the Globally Asynchronous Locally Synchronous (GALS) scheme is proposed. Recent years, Network-on-Chip (NoC) architectures which well realize the idea of GALS have been proposed to interconnect a large number of IP cores. NoC-based MPSoC is scalable, can be used in various fields.This paper describes the NoCOP (Network-on-Chip Open Platform) platform--an open platform for developing and verifying NoC-based MPSoC, which consists of software subsystem, hardware subsystem, design methodology, reusable hardware and software IPs.A communication hierarchy is designed to interconnect the NoCOP software subsystem and hardware subsystem. With the adoption of the communication hierarchy, it becomes easier to build new tools for the NoCOP platform. To verify the peripherals IPs and to enhance programmability, an instruction set simulator has been ported to the communication hierarchy.The NoCOP hardware subsystem is FPGA-based, which can hold designs with up to 2.0M ASIC gates. The NoCOP hardware subsystem consists of 12-layer PCB, following the main rules for high-speed design. Various resources can be found in the NoCOP hardware subsystem. Especially, requirements for HDTV1080P input/output are met. Two high-speed expansion sockets are offered to incorporate more resources or interconnect several hardware subsystems.Reusable NoC components are developed, such as switch, topology, routing algorithm and protocol. In the development of these NoC components, different implementations are compared. The NoC switch can achieve 3.2 GBytes/second data transfer rate in SMIC 0.18μm CMOS technology.NoC design can be verified on the NoCOP platform, using the NoCOP software subsystem and hardware subsystem. Adding a few new hardware IPs, a NoC monitoring framework can be built based on the NoCOP platform. It is useful to profile the NoC system.