Research Of Architecture For Network-on-chip Based On Dynamic Buffer Management

Multi-cores on chip has been the one of best solutions to improve computation performance with the increase of complex applications. Scalable packet-swithed Network on Chip(NoC) provides an efficient solution of multi-cors connection. It can remove the problems such as signal integrity, clock distribution, scaling communication architecture, productivity gap and so on. Efficient buffer management technologies can improve the performance and implementation cost of NoC network. This thesis focus on the research and implementation of high-performance-NoC with dynamic buffer management.This thesis firstly defines the NoC network architecture based on the key NoC architecture ingredient. And it proposes a wormhole network with dynamically allocated input queuing(DAIQ) swith. The network switch implements a novel switching allocation mechanism, namely, SRRM. Compared with virtual channel netwotk SAIQ, in which switch schedules at input packet level and output filt level, DAIQ network can obtain a good tradeoff between the performance and implementation cost. Additional, a VOQ network is proposed to support QoS. Additional,in order to solve the problem of clock distribution, an optimized mesochronous synchronizer is proposed in this thesis to support GALS framework.To improve the performance of network more, two dynamically buffered flow on-chip routers is proposed, namely, DAVC and DAVOQ. DAVC adoptes cut-through flow control and DAVOQ has a low latency pipeline logic. They are all based on traditional on-chip router with statically allocated virtual channel(SAVC), router SAVC schedules at input flit level and output filt level. Compared with router SAVC, router DAVC can obtain much more improving in network throughput and latency than a little cost in area and power with the same buffer capacity. While with the half buffer capacity, router DAVC can provides similar performance with the obvious savings of area and power consumption. Compared with router SAVC, router DAVOQ can improve the network performance and implementation cost with the same buffer capacity. Compared with router DAVC, router DAVOQ can provide latency decrease with a little throughput decrease.In order to evaluate and analyze the performance of communication architecture, this thesis constructs a NoC simulation platform with scalable network architecture and a NoC FPGA emulation prototype with configurable parameters. And it explores and analyzes the network performance of DAVC and DAVOQ under uniform traffic.