Implementation Of RS Encoder And Decoder Based On FPGA In Micro-satellite Communication

Developing and launching micro-satellite is one of the most important ways to serve the economy construction and benefit the people using space technology in our country. Modern micro-satellite has made quite great progress in the past decade for its own characteristics: light weight,small volume,lower cost,high performance, reliability and safety,celerity and agility and so on. In digital communication systems,digital signals will arouse error at the receiving port due to the effect of multi-path and various noises in the transmission channel. In terms of encoding and decoding,we can detect or get rid of these inevitable errors.In satellite communications,the channel encoder is used for error control. Based on the environment of space channel,we use the concatenated codes to encode the space data,which is recommended by Consultative Committee for Space Date System (CCSDS). The concatenated codes are composed of outer codes-RS Codes (255,223),interleave,inner codes—Convolutional Codes (2,1,7). The Reed-Solomon (RS) code is one of the most important non-binary cyclic codes of great correction ability. It can correct many burst errors,and has been widespread in space communications.The paper mainly focuses on the FPGA-oriented implementation of space channel coding according to the need of satellite channel encoding. Contribution includes:Analyzing the basic procedure of satellite channel encoding;Introducing the RS Codes encoding and decoding;Simulating those with SystemView and C, and analyzing the Anti-noise performance of RS code;Programming the encoding and decoding of RS (255,223) Codes with VerilogHDL;Simulating those with Modelsim;Realizing the RS encoder and decoder on FPGA development board .This work will be used in the satellite communication system designed by Nanjing University of Aeronautics and Astronautics for its resource saving,high reliability and low power consumption.