High-speed Design And FPGA Implementation Of Channel Encoder And Decoder For DVB-S2 Standard

The DVB-S2 standard uses the forward error correction coding scheme with BCH codes cascaded with LDPC codes.And this forward error correction code has a performance close to the Shannon limit.The LDPC codes with excellent error correction performance and highly parallel iterative decoding algorithm become the most powerful error correction codes in high-speed communication applications.With the increasing demand for various portable computing devices,the implementation of low-power chips has become extremely critical.Therefore,there is an increasing demand for low latency and low complexity hardware implementations of encoder and decoder in engineering practice.This thesis is according to the BVB-S2 standard as the research background,based on the theoretical analysis of LDPC codes and BCH codes,considering the direction of hardware implementation,designing the specific architecture for a high-speed encoder and decoder compatible with all code rates in the standard forward error correction codes scheme.Hardware circuit design with Verilog hardware description language,and using Vivado2018.3 as the simulation platform,based on Xilinx xcvu9 p chip for simulation and verification.For the BCH codes,the generator polynomial is firstly obtained from the minimal polynomial of the BCH codes based on the definition of the BCH codes in the DVB-S2 standard.Based on the coding principle,the division coding circuit based on the generating polynomial is used to design a four bits parallel calculation of the division coding circuit compatible with all code rates from the perspective of improving the throughput.Based on the BCH codes decoding principle,the Fi BM decoding algorithm is used to analyze and improve the four bits parallel computed decoding circuit by the serial decoding circuit.For the LDPC codes,the complete information of the parity-check matrix is calculated first by the compression information of the parity-check matrix given by the standard,and the obtained parity-check matrix has a dual-diagonal structure.The encoder is based on this dual-diagonal structure of the parity-check matrix and uses a forward recursive calculation method to realize a four bits parallel calculation.And the encoder compatible with all code rates.The encoder is designed to save storage resources by storing only the compressed information of the parity-check matrix,and the complete parity-check information is computed in real-time.The parity-check matrix is permuted by ranks and columns to obtain a matrix with a quasi-cyclic structure.When designing the decoder,based on this structure,the reading and writing order of the posterior probability messages of the variable nodes is optimized to reduce the decoding delay.Then the hardware structure is improved by considering the special submatrices in the parity-check matrix.The performance of different decoding algorithm parameters is analyzed comprehensively,and the layered min-sum algorithm is chosen to be used at 1/4 code rate,and the layered offset min-sum algorithm is chosen for other code rates.Combining the above,a complete decoder structure is designed to achieve a decoder compatible with all code rates.The final design of LDPC encoder and decoder can work stably at 200 MHz clock frequency,and the data throughput rate can reach up to 800 Mbps.Finally,the hardware test system is built and connected with the upper computer test and verification platform for joint testing and simulation to verify the correct design of BCH codes and LDPC codes encoder and decoder functions.The performance of BCH codes before and after cascading is compared,and it is proved that the cascaded BCH codes can effectively eliminate the error floor.