Design And FPGA Implementation Of Shortened-and-Punctured RS Encoder And Decoder In Wireless Channel

RS code is a kind of channel coding which has strong capability of error correction, especially for burst error correction. Due to its good performance of error correction, RS code has been widely used in deep space communication, data storage, mobile communication, DVB, WMAN and so on.Compared with other channels, the environments of wireless channels are very complicated. So signals may fade greatly when passing through wireless channels. Moreover, wireless channels have characteristics of time changing. So it is a deserved thesis to be researched in how to keep reliability and utility of wireless transmitting. Shortened-and-punctured RS codes can make encoding parameters configured flexibly according to channel characteristics. So, good balance can be gotten between transmitting reliability and utility using shortened-and-punctured RS codes.Firstly, considering about the above descriptions, usual encoding and decoding algorithms for RS codes are analyzed, especially for the MEA in this thesis.Due to the disadvantage of MEA that the number of iteration is not fixed ,a modified method is presented and this method can make the number of iteration fixed. Then, characteristics of wireless fading channels are analyzed from two aspects: Multipath Effect and Doppler Effect. Two classical wireless fading channel models: Rayleigh channel model and Rice channel model are presented. Based on the above analyzations, performance for error correction of shortened-and-punctured RS codes is simulated using C language. Channel and modulation are AWGN-BPSK and Rayleigh fading channel-DBPSK, respectively.The simulation shows that shortened-and-punctured RS codes can anti-fade in a certain extent. Lastly, the encoder which can support 6 shortened-and-punctured RS codes of RS(255,239) in IEEE 802.16d is designed and implemented in FPGA. Moreover, aiming at the shortage that traditional RS decoders can't correct erasures, a kind of decoder which can correct both errors and erasures using MEA is designed and implemented in FPGA. The decoder can run at 80MHZ stably.