Design Of RS(255,247) Encoder And Decoder Based On Verilog

Reed-Solomon code has made its position more and more important during error correcting codes because of its best coding efficiency and capability of error correction in the linear code. For now, it has been widely applied in the various fields. Along with the increasing demand for more high reliability and availability of transmission equipment and availability storage devices, the research and design of RS encoder and decoder has become more essential.RS (255,247) can be used for the error control system of some mass storage devices due to its large capacity of the encoded data. The design compiled by the Verilog can also be applied to other codec design implementation in this article written. The design process was introduced with the method of sub-structure so that this paper can better show the internal structure and function of RS encoding and decoding. The behavioral simulation and functional verification had been carried out for each structure in the article. What’s more, the simulation results of each module were also given.This paper introduces the theoretical basis of RS encoding and decoding in detail. During the procedure described in the RS decoding algorithm, the most complex structure, called the solution of the key equation module, had been compared with several algorithms which can be used of designing it. Finally, the non-inversion BM algorithm was used to calculate the solution of the key equation and the module had been completed. In the design of encoding, a kind of fast finite field multiplier was adopted which can speed up encoding. All the modules were designed by compiling the Verilog language and in addition the simulation verification of the RS (255,247) codec was given based on Field Programmable Gate Arrays.