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Encoding The Physical Channel Of LTE Based On FPGA

Posted on:2012-02-22Degree:MasterType:Thesis
Country:ChinaCandidate:L ZhangFull Text:PDF
GTID:2248330395487676Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of mobile communication,3G technology is developing, people for mobile communication requirements are increasingly high, however, the bottleneck of3G technology in some of its development has been severely hampered, so that the development of LTE(Long Term Evolution) has become the current hot topic. LTE’s proposed requirements for more stringent digital communications, communication system in order to ensure transmission reliability, widely used in the channel coding technique.With the continuous development of communication technology, data throughput communication services have become increasingly demanding, high-speed data communications to meet the requirements of communication systems now use the hardware encoder for data processing.This paper introduces two common encodings are:tail biting convolutional code and Turbo code. Analysis of the basic components,the structure of both principle,the advantages and disadvantages. Then, based on LTE protocol, to understand the actual LTE protocol encoding specifications and requirements. For data input and output, ports and parameters have clearly defined, in the realization of the process to be processed according to protocol. Finally, the paper realization tail biting convolutional code and Turbo code for the FPGA design, the function of the encoder module division, then the timing of the various sub-modules and functions described in detail, with the final hardware description language description. Simulation and synthesis results show that the encoder can process the data well and get good results. And takes fewer resources, smaller delay, higher throughput can be used in the actual work environment. The codes are described using VHDL language, using the analysis of ISE, Modelsim simulation, and Xilinx series Virtex6series chip implementation. The innovation of this paper is achieved using Turbo coding look-up table method that can reduce the computational complexity, reduce cycle time and save storage space. This paper only involved encoder without considering the realization the decoder, possibly the decoder seems complicated because the structure of encoder when realize decoding, so should change the structure of the encoder.This place is need improved in future work.
Keywords/Search Tags:LTE, Tail biting convolutional code, Turbo code, FPGA, Encoder
PDF Full Text Request
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