Research And FPGA Implementation Of TPC Encoder And Decoder In S-band Satellite TT&C System

Channel coding is an error control technology that is being applied in signal transmission,and it is an indispensable part of satellite communication system.Turbo product code(TPC),as a forward error correction channel coding,is widely used in various communication scenarios due to its simple coding structure,low decoding complexity and strong error control performance.The direction of researchers' efforts is how to maintain excellent error control performance while reducing complexity and improving decoding throughput.In this paper,the Chase-Pyndiah algorithm is improved,and the TPC encoder and decoder with low resource occupation and high throughput applied to the S-band satellite TT&C system are realized based on the Field Programmable Gate Array(FPGA)platform.Firstly,the hardware design of the TT&C equipment board is completed in this paper,which provides a hardware platform for TPC encoder and decoder.According to the requirements of the signal rate,bandwidth,frequency and bit error rate parameters in the technical protocol,two hardware architectures of satellite TT&C equipment board are proposed.After analyzing and comparing the performance,power consumption and cost,the zero intermediate frequency architecture is selected.Then,The Compact PCI Express interface circuit,Double Data Rate SDRAM(DDR)circuit,AD9361 peripheral circuit and FPGA peripheral circuit in the architecture are designed respectively.Secondly,the structure of TPC encoder and decoder is designed.By analyzing the coding structure of TPC and several commonly used component codes,(64,57)extended Hamming code is selected as the component code of TPC.Then,this paper analyzes the hard decision decoding algorithm and soft decision decoding algorithm of TPC,and compares the serial structure and parallel structure of iterative soft decision decoding.Combined with several factors affecting iterative decoding,a TPC decoder structure with dynamically adjusting the number of iterations is proposed.Finally,the FPGA logic software of TPC encoder and decoder is designed based on Verilog language in Vivado development environment,and the functions of encoder and decoder are verified in Vivado Simulator.The TPC encoder with a coding rate of 40 Mbps is implemented at 40 MHz clock frequency,and the TPC decoder achieves a decoding rate of 24.85Mbps?40.12 Mbps varying with the channel SNR at 200 MHz clock frequency.Under the condition of Eb/N0=12d B required by the technical protocol,the decoding rate is40.12 Mbps.Then,the hardware platform is verified on the designed satellite TT&C equipment board,and no error code is found after 2 hours of test,which meets the technical requirements.