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Design Of High Performance Reed-Solomon Encoder And Decoder And Its Implementation In FPGA

Posted on:2011-08-07Degree:MasterType:Thesis
Country:ChinaCandidate:M KangFull Text:PDF
GTID:2178360305453017Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
The complications of the design of multiplier in different basises are discussed in this thesis. Multiplier has the biggest complexity and the longest time delay in Galois Field, so the design of multiplier is the most important part in the design of Reed-Solomon encoder and decoder, thus the differences of the design of RS encoder and decoder in different basises are mostly reflected by the differences of the design of the multiplier in different basises.The design of RS(255.239) encoder and decoder are completed in this thesis, and the design of the encoder contains the module of multiplication, addtion, shift register of eight bit parallel in and parallel out, counter of module 256,and multiplexer. The algorithm of Berlekamp iteration is used to solve the key equation, the algorithm of chien is used to solve the error location polynomialσ(x), the algorithm of Forney is used to get the error pattern, and in the end the output of the decoder is presented. The hardware configuration of RS(255,239) encoder and decoder is designed in VHDL,and downloaded into FPGA.
Keywords/Search Tags:error correcting code (ECC), RS code, Galois Field(GF), polynomial basis, normal basis, dual basis
PDF Full Text Request
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