Design And Implementation Of Hardware For Reconfigurable Computing Hybrid System

As the rapid development and wide applicationg of the reconfigurable computing technology,in the the reconfigurable computing system has become the foucus on industrial community.In high-performance computing field with compute-intensive applications, the industry has been fully aware of reconfigurable computing has great potential. Reconfigurable computing devices are set high performance, easy to modify and can be repeated use of the fine features in one, not only for the current high-performance computing have a major impact, but also an urgent need for the operating system to support real-time dynamic reconfiguration of resources hybird scheduling to better play to their strengths.However, in a dynamic reconfigurable system, the software tasks running on the embedded processor and hardware tasks on the FPGA as two independent parts, lack of a unified management system, In addition, the limitations of traditional software and hardware also greatly limits the wider application of this technology. Therefore,to provide a unified hardware and software programming interface became the urgent need to address the problem. For this problem, this paper designed a generic model of the hardware task, the model of the upper layer software provides a unified interface, easy to carry out further upper layer software package, thus the upper user in the system development to provide a great convenience.The ICAP controller which is responsible for downloading the bit stream of Re-configuration of hardware tasks to support reconfigurable computing device hybrid system is another important component. The traditional OPB-HWICAP ICAP controller control the whole download process by software, and the CPU must be involved throughout the process of moving data, efficiency is very low, thus affecting the efficiency of the whole system.To the problem of the traditional OPB-HWICAP ICAP controller,this system made a corresponding improvement on it. To replace the time consuming part which to move data by the DMA hardware to achieve.thereby reducing the burden on the system CPU so the CPU can be more time for software processing tasks which improve the overall system efficiency. In this thesis, the task of the general model using hardware AES encryption algorithm will be packaged, the hardware tasks to verify the feasibility of the model and the experiment will be the task of hardware and software implementation of AES encryption algorithm AES efficiency compared to verify the task such as AES encryption algorithms of computing tensive tasks in hardware to achieve great advantage. In addition, this thesis also compared the traditional OPB-HWICAP ICAP controller and the ICAP controller in this thesis in downloading efficiency and CPU occupancy to verify the ICAP controller in this thesis is better..