Design Of 12bit 50MSPS PIPELINE ADC

Analog to digital converters is the bridge of the analog signal in the real-life world to digital signal。Pipeline ADC is a with high- resolution,high speed and low power dissipation structure , which have a wide variety of applications,such as High Definition Audio and Video Signal Processing and Wireless Communication systems.This purpose of thesis submitted a design of a 12-bit 50 MSPS pipeline ADC, based on a 0.18μm SMIC CMOS process, which can be used in the field of video and audio instruments and the sample of intermediate frequency transceiver of communication. We did much work in the system architecture design and the transistor level module circuit design. A eleven stage pipeline architecture was used in this design: the preliminary ten stages 1.5 bit per-stage sub ADC, and the last stage is an 2 bit flash ADC. These eleven stages formed the ADC core. We accomplished the sub module circuits design, such as high resolution sample and hold circuit,high gain wide bandwidth operational Tran conductance amplifier, 1.5 bit per stage sub ADC, digital correction circuit, clock stabilization circuit, the transistor level band gap. Non-ideal factors in pipeline ADC are analyzed and some methods to decrease these non-ideal factors are presented. Selected the best capacitor by analyses ,so as to get the least layout area and low power dissipation。The simulation results with cadence Spetre show that the circuit can get 11.35bit resolution.