Design And Implementation Of Image Compression System Based On FPGA

With the high-speed development of information and computer technology, Digital Signal Processing technology has been a very key science gradually. As an important modern technology, image processing has been used widely in such fields as communication, spaceflight aviation, remote sensing telemetering measurement, biomedicine, military, information safety, etc. Image processing, especially real-time processing technology for image with high-resolution, has great meaning to the development of related fields. Furthermore, the combination of FPGA (Field Programmable Gate Array) and Verilog HDL has greatly improved the designing method for electronic system and shortened the duration, which offers hardware and software supports to the implementation of image compression system.The main work of this paper is:(1)The paper designs an image compression system based on FPGA, which selects XILINX Virtex-ⅡPro chips as hardware core, MICRON MT48LC4M16A2 SDRAM as memory chip and JPEG-LS as compression arithmetic.(2)Implement the basic arithmetic of JPEG-LS standard based on Verilog HDL. Other members in our group can get many supports from this design.(3)Design and implement the SDRAM controller based on Verilog HDL. From it, other components of this image compression system can access memory chip flexibly.(4)Set up a test platform for image compression system based on FPGA. Using the platform, test the results of SDRAM controller module and the function of JPEG-LS arithmetic. The results show that design described in this paper can work correctly.