SCSP Products QV Test Flow Optimization

Semiconductor memories play an important role in modern System-on-Chip (SoC) designs, including RAM and Flash memory. Even as memory requirement grew dramatically in recent year, size of memory package still lightly decreases. Stacking flash and RAM into one device make it possible to implement higher density, and diverse memory component in small single package. This is what we call SCSP (Stacked Chip Scale Package). Semiconductor memory testing thus has been a key problem in testing integrated circuits for years. With their growing density and capacity, the test time grows rapidly if the test methodologies and equipments remain the same. Test time reduction other than parallel insertion—which is expensive and more and more difficult to keep up with the memory capacity growth—is a long time researched issue, as test cost is directly related to the time each product stays on the tester. In this thesis, we focused on test time reduction, and proposed one optimized test program by shortening and eliminating test blocks. In the early stage of SCSP product development, we applied the full QV(Quality and Validation) test suit for each product QV process. Along with the product qualification purpose change, we need focus more on SCSP specific problem, like package related issue. This thesis is devoted to two parts solving SCSP testing issues discussed above. One is based on the understanding of each QV test program blocks to identify the test time reduction candidates, and then provided the best proposal of optimized test program for test time reduction without quality issues. The other is experiment design and implementation for optimized test program, meeting goals of test time reduction by 60%, DPM control for quality and cost savings by 2 million dollars. This testing plan provided in this paper has practical value.