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Flash Memory Test Optimization

Posted on:2010-09-03Degree:MasterType:Thesis
Country:ChinaCandidate:C J TaoFull Text:PDF
GTID:2298360275470823Subject:Software engineering
Abstract/Summary:PDF Full Text Request
It is well known that Flash memory development speed is beyond people’s imagination, whatever Flash density or Flash speed. Test is, then, playing a more and more important role because product density and complexity requires longer and longer test time, as a result there will be higher requirement to test equipment. Test is always very expensive in semiconductor industry. Test does not contribute to product quality, so it’s a non-value added station in the whole production line. Test purpose is to detect failed units, to find a way to improve process hole and minimize the negative impact to final customer or improve productivity. Engineers are facing many challenges in Flash memory development and test. To provide low cost high quality product, test cost has to be reduced consistently. It’s difficult for expensive equipment to upgrade along with product development, furthermore, upgrade itself is also very expensive, so upgrade is generally not a good way for test time reduction.This thesis is based on product analysis plus test pattern optimization, other than equipment upgrade, to reduce test time. Comparing to European and American market, due to early Flash memory development there are most advanced test equipment and test methodology. It’s described in many articles that test time reduction can be achieved through test pattern design, but due to different product design, optimization method could be different accordingly. Anyway, test pattern optimization is becoming a popular way for test time reduction in Flash memory or even whole semiconductor industry.Research is focusing on product, test flow and major failure modes analysis, to design most effective test pattern to reduce test time, save expensive test cost. Test cost saving is always considered as first priority in factory. Furthermore, due to floor space limitation it’s impossible to accommodate more test equipments. Implementation of this thesis, is to improve test productivity without adding more test equipments and cost.
Keywords/Search Tags:Flash Memory, TTR, Test Pattern, Read, Write, Program, Erase, Failure Mode
PDF Full Text Request
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