Points Gate Flash Memory Failure Mechanism Research And Performance Improvement Method

As one of the nonvolatile semiconductor memories, the split-gate flash memory has the advantages of high program efficiency, low erase voltage and immunity to over-erasing, therefore, the corresponding peripheral control circuits are simple. Since its invention, the split-gate flash memory has been extensively used in the fields of low density code storage and embedded flash memory. The manufacturing process of split-gate flash memory is relatively complex because both flash cell and logic devices must be integrated during processing, thus engineers need do process improvement and optimization based on the feedback from yield data and the root cause of different failures, it is meaningful to study the failure mechanism of split-gate flash memory.In this thesis the device structure, cell working principle, manufacturing flow and testing flow of0.18μm self-aligned split-gate flash memory were introduced. Based on the analysis of electrical failure analysis data and the program/erase model, the common failures of split-gate flash (including erase fail, programming fail and program-disturb fail) were classified and investigated, physical failure analysis data for different type of failures were presented to prove the failure mode.The working windows of programming and program-disturb are restraining from each other, a method was introduced to evaluate the programming window of split-gate flash in this thesis. The programming window of a flash memory product was optimized by doing experiment at VSS IMP step. In this experiment, the best doping condition was obtained to make the process window match to CP testing condition which was fixed, therefore process window was enlarged and yield was stabilized.