Research On Validation Test And Failure Analysis Of VLSI Chip

The validation test has been a necessary and important process, which assumes the double task in checking the correctness of both the design and test programs. Failure analysis is a main aspect of the validation test and it provides the fundamental ways for tracing the failure mechanisms and optimizing the validation test flow. Today the validation test faces the increasing challenges and with the development of the semiconductor technology it has involved many fields, such as the design, manufacture, and so on. To develop a general validation test strategy with low cost and high efficiency has been a new focused issue. To the problems in the validation test project of the Godson chip in the I.C.T, C.A.S.1, we have got the following achievements on the test development flow, the failure analysis flow, etc.1. For the problems in the test of this chip, such as high-frequency, rigorous timing, high-volume data, limited test capacity of a single test method, high test cost, etc. we set up a feasible validation test and analysis flow. In this flow a tradeoff of multiple test methods is adopted, which includes structural test, functional test and parametric test. Using the test mode of"stop as finding the fault"and based on the position of the first failure, we can label the faulty chips into different bins. Based on the information of the test item efficiency and test resources, we design an algorithm to optimize the validation test flow. Compared with the exhaustive algorithm (n!) and dynamic programming algorithm ( O ( dn2n)), its computing complexity is decreased to O(dn3)( d is the number of circuits tested, and n is the number of test items to be ordered ) .2. Based on the characterization analysis such as shmoo plot, etc. we make some objective analysis on the test items and the speed-related faults by using different experiments. As the experimental data showed, the coverage areas of each test item are not mutually contained. So to guarantee the better validation test quality, we must introduce a tradeoff of multiple test methods to make test items supplemented each other. We also find that the probability of the faulty chips found is increased as we increase the test frequency. It is proved that those speed-related faults are more active in the environment of high frequency and the high-speed test (e.g. at-speed test) is a necessary test item in the validation test.3. For the traditional"serial-mode"test development flow of this chip has such disadvantages as low-efficiency, long-period, lack of intercommunication, etc., we propose a"parallel-mode"flow. This flow makes the development of the validation test parallel with the manufacture test and enhances the intercommunication capacity between designers, test engineers and manufacture engineers, which not only eases the information share of the design, test programs and the test vectors, but also can earlier finish the test vector debugging and related test configurations before the tape-out. Thus both the validation test and the manufacture test can start earlier and the whole test development period is shortened largely.