Signal Integrity Issues Study In Stacked-up Chip Scale Packaging Design

Nowadays, consumptive electronic products have developed quickly, by theincrease of clock frequency, discovering and resolving signal integrity issuesis more and more important. An electrical guide line which balance signalintegrity, manufacturability and cost is very helpful for product packagingdesign.This paper finds out the way of optimizing signal integrity issues inStacked-up Chip Scale Package by packaging design, including shorten tracelength, increase trace width and spacing, connect power/ground nets, datatrace length matching, branch length matching, clock signal shielding andminimize return path, etc.After theoretical analyzing, certain assumption and parameter definition, theauthor designs testing circuits on her own, draws substrate layout, created3D model, extracts model parameters, compiles testing code and analyzedwave and result data, finally makes conclusion of the exact range of datatrace matching and branch trace length matching which could make thesignal integrity issues acceptable. This is a keynote to package designengineers as it improves the signal integrity performance of product andshortens the development period. Also, the actual impact of clock signalshielding and return path minimization is found out by simulation. Itbecomes the convincing reference for package design, and helps designengineer to make decision of whether to increase the manufacture cost.