One Example Of High Performance Memory BIST Design

As the area ratio of embedded memory versus logic circuit in a SOC design increases, a high quality memory test methodology becomes extremely important. Memory Built-In Self-Test (BIST) technology has been the standard memory test methodology, since it can test single memory with high coverage to enhance product quality and yield, with a reasonable area overhead. The high performance memory brings up the challenge to BIST circuit design for at-speed test. The paper proposes an FSM structure optimization method. The optimized BIST circuit achieves better speed and area performance than the traditional designs.